The present invention relates to a semiconductor memory device containing an error correcting code circuit (ECC circuit).
In accordance with recent increase in the storage capacity of a semiconductor memory device, the probability of failure occurring in any of memory elements included in the semiconductor memory device or the probability of error write and error read has been increased. Therefore, an ECC circuit-containing semiconductor memory device having a function to detect a data error from an electric signal and correct the detected error has been proposed.
An ECC circuit has an error correcting function designed on the basis of a coding theory. An error is corrected through encoding as follows: Information to be originally transferred is sent with redundancy added in accordance with a given rule, and a receiver checks whether or not the received information accords with the rule, so as to detect and correct an error in accordance with the result of the check. Therefore, in an ECC circuit-containing semiconductor memory device, in order to improve its reliability, redundancy is added to digital information so as to be processed more easily and systematically with a machine.
As an example of the conventional technique, an ECC circuit-containing semiconductor memory device and its operation disclosed in Japanese Laid-Open Patent Publication No. 5-54697 will now be described with reference to FIGS. 10 and 11.
FIG. 10 is a block diagram for schematically showing the structure of the conventional ECC circuit-containing semiconductor memory device (hereinafter referred to as the first conventional example) described in the publication and corresponding to the background of this invention. As is shown in FIG. 10, an ECC circuit memory block 101 includes a data storage area 102, an error correcting code storage area 103, an error correcting code generator 104, a decoder 105 and an I/O control circuit 106.
The I/O control circuit 106 sends a data input through an I/O data line 112 from a device externally provided to the ECC circuit memory block 101 to the data storage area 102 and the error correcting code generator 104 through an input data line 107. The error correcting code generator 104 receives the input data from the input data line 107, generates an error correcting code corresponding to the input data, and inputs the generated error correcting code to the error correcting code storage area 103 through an error correcting code line 108. The decoder 105 fetches a data read from the data storage area 102 through a read data line 109, and fetches an error correcting code read from the error correcting code storage area 103 through a read error correcting code line 110. When the fetched data has no error, the decoder 105 sends the data to the I/O control circuit 106 through an output data line 111, and when the data has an error, the decoder 105 sends a corrected data to the I/O control circuit 106 through the output data line 111. The I/O control circuit 106 outputs the data output from the decoder 105 to a device externally provided to the ECC circuit memory block 101 through the I/O data line 112.
Now, an operation to write a data in the ECC circuit memory block 101 and an operation to read a data from the ECC circuit memory block 101 will be described in details by exemplifying a case where one word consists of an 8-bit data and a 4-bit error correcting code.
First, in writing a data in the ECC circuit memory block 101, an 8-bit data, (D0, D1, D2, D3, D4, D5, D6, D7), input through the data I/O line 112 from the external device is fetched by the I/O control circuit 106. This 8-bit data is written through the input data line 107 in the data storage area 102 by the I/O control circuit 106 and is also input to the error correcting code generator 104.
Next, the error correcting code generator 104 generates a 4-bit error correcting code, (C0, C1, C2, C3), corresponding to the input 8-bit data, and the error correcting code is written through the error correcting code line 108 in the error correcting code storage area 103. At this point, in the method described in the aforementioned publication, respective elements of the error correcting code, i.e., C0, C1, C2 and C3, are generated in accordance with the following Formulas (1):
Formulas (1):C0=D0+D1+D3+D4+D6C1=D0+D2+D3+D5+D6C2=D1+D2+D3+D7C3=D4+D5+D6+D7In Formulas (1) and the following description, a symbol “+” indicates an exclusive OR.
Next, in reading a data from the ECC circuit memory block 101, the decoder 105 fetches an 8-bit data, (D0′, D1′, D2′, D3′, D4′, D5′, D6′, D7′), read from the data storage area 102 through the read data line 109 and a 4-bit error correcting code, (C0′, C1′, C2′, C3′), read from the error correcting code storage area 103 through the read error correcting code line 110. The decoder 105 then generates a 4-bit syndrome, (S0, S1, S2, S3), in accordance with the following formulas:S0=C0′+D0′+D1′+D3′+D4′+D6′S1=C1′+D0′+D2′+D3′+D5′+D6′S2=C2′+D1′+D2′+D3′+D7′S3=C3′+D4′+D5′+D6′+D7′
Then, in order to correct an error of each bit of the read 8-bit data, the decoder 105 inverts a bit detected as an error in the data, (D0′, D1′, D2′, D3′, D4′, D5′, D6′, D7′), corresponding to the bit string of the syndrome, and outputs the resultant data to the output data line 111.
At this point, the data corresponding to the bit string of the syndrome (namely, a test matrix H) is represented by the following Formula (2):
Formula (2):   H  =      (                            1                          1                          0                          1                          1                          0                          1                          0                          1                          0                          0                          0                                      1                          0                          1                          1                          0                          1                          1                          0                          0                          1                          0                          0                                      0                          1                          1                          1                          0                          0                          0                          1                          0                          0                          1                          0                                      0                          0                          0                          0                          1                          1                          1                          1                          0                          0                          0                          1                      )  When s=(S0, S1, S2, S3), the syndrome s is represented as follows:s=(D0′,D1′, . . . ,D7′,C0′, . . . ,C3′)HTIt can be confirmed through vector calculation that the syndrome s does not includes information of the data itself but includes information of an error bit alone.
FIG. 12 is a table for showing the relationship between an error bit and a syndrome, which simply explains the meaning of Formula (2) above.
For example, when S0=1, S1=1, S2=1 and S3=0, the data of bit D3′ is found to be an error, and hence, the data of this bit is corrected. On the other hand, when S0=S1=S2=S3=0, there is no error in the data, and hence, no bit data is inverted.
The 8-bit data resulting from this error correction is output to the output data line 111, so as to be output from the I/O control circuit 106 through the I/O data line 112 to the device externally provided to the ECC circuit memory block 101.
In this manner, a data is written in or read from the ECC circuit memory block 101.
Next, the structure and the operation of another semiconductor memory device containing an ECC circuit designated as a second conventional example will be described. FIG. 11 is a block diagram for schematically showing the structure of the semiconductor memory device disclosed in the aforementioned publication.
Since the ECC circuit of FIG. 10 alone is inconvenient for conducting a process other than the predetermined error correction, this device is improved for conducting various types of error corrections in consideration of the characteristics of the semiconductor memory device.
As is shown in FIG. 11, the semiconductor memory device of the second conventional example includes, in addition to the composing elements of the semiconductor memory device of FIG. 10, an error correcting code I/O control circuit 113.
In the circuit of FIG. 11, a test mode signal 117 is set to “0” in a general operation. Thus, a data can be written in and read from the ECC circuit memory block 101 in the same manner as in the operation of the first conventional example described above.
Next, an operation in a test mode will be described. When the test mode signal 117 is set to “1”, selector gates 114 through 116 are controlled in accordance with the test mode signal 117. As a result, a data is written in the data storage area 102 by the I/O control circuit 106 through the input data line 107. Also, a data read from the data storage area 102 is output to the I/O control circuit 106 through the read data line 109 and the selector gate 114. In this case, the error correcting code generator 104 and the decoder 105 are not concerned with the data read/write operation, and hence, a data can be written in or read from the data storage area 102 through neither the error correcting code generator 104 nor the decoder 105, namely, directly.
On the other hand, an error correcting code, (C0, C1, C2, C3), is written in the error correcting code storage area 10 through the error correcting code I/O control circuit 113 and the selector gate 115 by a device externally provided to the ECC circuit memory block 101. Also, a data read from the error correcting code storage area 103 is output to a device externally provided to the ECC circuit memory block 101 through the selector gate 116 and the error correcting code I/O control circuit 113. In this manner, a data can be written in or read from the error correcting code storage area 103 directly.
In this manner, in the ECC circuit-containing semiconductor memory device of the second conventional example, errors of two or more bits are corrected by testing memory cells included in the data storage area 102 and the error correcting code storage area 103 by using, for example, checker pattern test data. This device is thus improved to be determined as a good product or a defective product.
The first and second conventional examples, however, have the following problems:
In the first conventional example, in the case where different test patterns (such as a checker pattern) should be respectively used for testing the data storage area and the error correcting code storage area, the test cannot be rapidly carried out.
In the second conventional example, although test patterns can be variously changed, the area occupied by the entire semiconductor memory device is increased on the contrary. Therefore, it is difficult to sufficiently meet demand for compactness of electronic equipment including the semiconductor memory device.
Furthermore, in the structure shown in FIG. 10 or 11, there is no means for testing an operation for correcting an error of the decoder 105, and there is a possibility that a 1-bit error cannot be accurately corrected. In other words, the reliability of an ECC circuit-containing semiconductor memory device cannot be sufficiently guaranteed by the conventional test method.